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publication number s29jl064h_00 revision a amendment 8 issue date september 8, 2009 s29jl064h s29jl064h cover sheet 64 megabit (8 m x 8-bit/4 m x 16-bit) cmos 3.0 volt-only, simultaneous read/write flash memory data sheet for new designs involving fine-pitch ball grid array (fbga) packages, s29pl064j supersedes s29jl064h and is the factory recommended migration path. please refer to the s29pl-j da ta sheet for specifications and ordering information. notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
publication number s29jl064h_00 revision a amendment 8 issue date september 8, 2009 distinctive characteristics architectural advantages ? simultaneous read/write operations ? data can be continuously read from one bank while executing erase/program functions in another bank ? zero latency between read and write operations ? flexible bank architecture ? read may occur in any of the three banks not being written or erased ? four banks may be grouped by customer to achieve desired bank divisions ? boot sectors ? top and bottom boot sectors in the same device ? any combination of sectors can be erased ? manufactured on 0.13 m process technology ? secured silicon sector: extra 256-byte sector ? factory locked and identifiable: 16 bytes available for secure, random factory electronic serial number; verifiable as factory locked through autoselect function ? customer lockable: one-time programmable only. once locked, data cannot be changed ? zero power operation ? sophisticated power management circuits reduce power consumed during inactive periods to nearly zero ? compatible with jedec standards ? pinout and software compatible with single-power-supply flash standard package options ? 63-ball fine pitch bga ? 48-pin tsop performance characteristics ? high performance ? access time as fast as 55 ns ? program time: 4 s/word typical using accelerated programming function ? ultra low power consumption (typical values) ? 2 ma active read current at 1 mhz ? 10 ma active read current at 5 mhz ? 200 na in standby or automatic sleep mode ? cycling endurance: 1 million cycles per sector typical ? data retention: 20 years typical software features ? supports common flash memory interface (cfi) ? erase suspend/erase resume ? suspends erase operations to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ? data# polling and toggle bits ? provides a software method of detecting the status of program or erase cycles ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences hardware features ? ready/busy# output (ry/by#) ? hardware method for detecting program or erase cycle completion ? hardware reset pin (reset#) ? hardware method of resetting the internal state machine to the read mode ? wp#/acc input pin ? write protect (wp#) function protects sectors 0, 1, 140, and 141, regardless of sector protect status ? acceleration (acc) function accelerates program timing ? sector protection ? hardware method to prevent any program or erase operation within a sector ? temporary sector unprotect allows changing data in protected sectors in-system s29jl064h 64 megabit (8 m x 8-bit/4 m x 16-bit) cmos 3.0 volt-only, simultaneous read/write flash memory data sheet
4 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 simultaneous read/write operations with zero latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 s29jl064h features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2. product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4. connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8. device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 word/byte configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.2 requirements for reading array data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.3 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.4 simultaneous read/write operations with zero latency . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.5 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.6 automatic sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.7 reset#: hardware reset pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 8.8 output disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.9 autoselect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.10 sector/sector block protection and unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.11 write protect (wp#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.12 temporary sector unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.13 secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.14 hardware data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9. common flash memory interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10. command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.1 reading array data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.2 reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.3 autoselect command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.4 enter secured silicon sector/exit secured sili con sector command sequence . . . . . . . . . 32 10.5 byte/word program command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.6 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.7 sector erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.8 erase suspend/erase resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11. write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.1 dq7: data# polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.2 ry/by#: ready/busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.3 dq6: toggle bit i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.4 dq2: toggle bit ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.5 reading toggle bits dq6/dq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.6 dq5: exceeded timing limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.7 dq3: sector erase timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13. operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 14. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 14.1 cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 14.2 zero-power flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15. test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 16. key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
september 8, 2009 s29jl064h_00_a8 s29jl064h 5 data sheet 17. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 17.1 read-only operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 17.2 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 17.3 word/byte configuration (byte#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 17.4 erase and program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 17.5 temporary sector unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 17.6 alternate ce# controlled erase and program operations . . . . . . . . . . . . . . . . . . . . . . . . . . 54 18. erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 19. tsop & bga pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 20. physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 20.1 fbe063?63-ball fine-pitch ball grid array (bga) 12 x 11 mm package . . . . . . . . . . . . . . 57 20.2 ts 048?48-pin standard tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 21. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet figures figure 4.1 48-pin standard tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4.2 63-ball fine-pitch bga (fbga) - top view, balls fa cing down . . . . . . . . . . . . . . . . . . . . . . 11 figure 8.1 temporary sector unprotect operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8.2 in-system sector protect/unprotect algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 8.3 secured silicon sector protect verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10.1 program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 10.2 erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 11.1 data# polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 11.2 toggle bit algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 12.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 12.2 maximum positive overshoot wavefo rm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 14.1 i cc1 current vs. time (showing active and automatic s leep currents) . . . . . . . . . . . . . . . . 44 figure 14.2 typical i cc1 vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 15.1 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 16.1 input waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 17.1 read operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 17.2 reset timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 17.3 byte# timings for read operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 17.4 byte# timings for write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 17.5 program operation timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 17.6 accelerated program timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 17.7 chip/sector erase operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 17.8 back-to-back read/write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 17.9 data# polling timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 17.10 toggle bit timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 17.11 dq2 vs. dq6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 17.12 temporary sector unprotect timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 figure 17.13 sector/sector block protect and unprotect timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 17.14 alternate ce# controlled write (erase/program) o peration timings . . . . . . . . . . . . . . . . . . 55
september 8, 2009 s29jl064h_00_a8 s29jl064h 7 data sheet tables table 8.1 s29jl064h device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8.2 s29jl064h sector architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 8.3 bank address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8.4 secured silicon sector addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8.5 s29jl064h autoselect codes, (high voltage method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8.6 s29jl064h boot sector/sector block addresses for protection/unprotection . . . . . . . . . . . 22 table 8.7 wp#/acc modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9.1 cfi query identification string. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 9.2 system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 9.3 device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9.4 primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 table 10.1 s29jl064h command definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 11.1 write operation status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 15.1 test specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 1. general description the s29jl064h is a 64 megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. word mode data appears on dq15?dq0; byte mode data appears on dq7?dq0. the device is designed to be pr ogrammed in-system with the standard 3.0 volt v cc supply, and can also be programmed in standard eprom programmers. the device is available with an access time of 55, 60, 70, or 90 ns and is offered in 48-pin tsop and 63-ball fine pitch bga packages. standard control pins?chip e nable (ce#), write enable (we#), and output enable (oe#)?control normal read and write operat ions, and avoid bus contention issues. the device requires only a single 3.0 volt power supply for both read and write functions. internally generated and regulated voltages are provi ded for the program and erase operations. 1.1 simultaneous read/write operations with zero latency the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into four banks, two 8 mb banks with small and large sectors, and two 24 mb banks of large sectors. sector addresses are fixed, system software can be used to fo rm user-defined bank groups. during an erase/program operation, any of the three non-busy banks may be read from. note that only two banks can operate simultaneously. the device can impr ove overall system performance by allowing a host system to program or erase in one bank, then immediat ely and simultaneously read from the other bank, with zero latency. this releases the syst em from waiting for the completion of program or erase operations. the s29jl064h can be organized as both a top and bottom boot sector configuration. 1.2 s29jl064h features the secured silicon sector sector is an extra 256 byte sector capable of being permanently locked by spansion or customers. the secured silicon customer in dicator bit (dq6) is permanently set to 1 if the part has been customer locked, and permanently set to 0 if th e part has been factory locked. this way, customer lockable parts can never be used to replace a factory locked part. factory locked parts provide several options. the secured silicon sector may store a secure, random 16 byte esn (electronic serial nu mber), customer code (programmed through spansion programming services), or both. customer lockabl e parts may utilize the secured silic on sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. dms (data management software) allows systems to easily take advant age of the advanced architecture of the simultaneous read/write product line by allowing removal of eepr om devices. dms will also allow the system software to be si mplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. to write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. this is an advan tage compared to system s where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the flash memory device (or memory devices), and more . using dms, user-written software does not need to interface with the flash memory direct ly. instead, the user's software accesses the flash memory by calling one of only six functions. the device offers complete compatibility with the jedec 42.4 single-power-s upply flash command set standard . commands are written to the command register using standard microprocessor write timings. reading data out of the device is similar to reading from other flash or eprom devices. bank megabits sector sizes bank 1 8 mb eight 8 kbyte/4 kword, fifteen 64 kbyte/32 kword bank 2 24 mb forty-eight 64 kbyte/32 kword bank 3 24 mb forty-eight 64 kbyte/32 kword bank 4 8 mb eight 8 kbyte/4 kword, fifteen 64 kbyte/32 kword
september 8, 2009 s29jl064h_00_a8 s29jl064h 9 data sheet the host system can detect whether a program or er ase operation is comple te by using the device status bits: ry/by# pin, dq7 (data# polling) and dq6/dq2 (toggl e bits). after a program or erase cycle has been completed, the device automatically returns to the read mode. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of t he sectors of memory. this can be ac hieved in-system or via programming equipment. the device offers two power-saving features. when add resses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both modes. 2. product selector guide part number s29jl064h speed option standard voltage range: v cc = 2.7?3.6 v 55 60 70 90 max access time (ns), t acc 55 60 70 90 ce# access (ns), t ce 55 60 70 90 oe# access (ns), t oe 25 25 30 35
10 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 3. block diagram v cc v ss bank 1 address bank 2 address a21?a0 reset# we# ce# byte# dq0?dq15 wp#/acc state control & command register ry/by# bank 1 x-decoder oe# byte# dq15?dq0 status control a21?a0 a21?a0 a21?a0 a21?a0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 mux mux mux bank 2 x-decoder y-gate bank 3 x-decoder bank 4 x-decoder y-gate bank 3 address bank 4 address
september 8, 2009 s29jl064h_00_a8 s29jl064h 11 data sheet 4. connection diagrams figure 4.1 48-pin standard tsop figure 4.2 63-ball fine-pitch bga (fbga) - top view, balls facing down 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 a18 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 c2 d2 e2 f2 g2 h2 j2 k2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 c5 d5 e5 f5 g5 h5 j5 k5 c6 d6 e6 f6 g6 h6 j6 k6 c7 d7 a7 b7 a8 b8 a1 b1 a2 e7 f7 g7 h7 j7 k7 l7 l8 m7 m8 l1 l2 m1 m2 nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* dq15/a-1 v ss byte# a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 a21 reset# we# dq11 dq3 dq10 dq2 a20 a18 wp#/acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 * balls are shorted together via the substrate but not connected to the die.
12 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 5. pin description 6. logic symbol a21?a0 22 addresses dq14?dq0 15 data inputs/outputs (x16-only devices) dq15/a-1 dq15 (data input/output, word m ode), a-1 (lsb address input, byte mode) ce# chip enable oe# output enable we# write enable wp#/acc hardware write pr otect/acceleration pin reset# hardware reset pin, active low byte# selects 8-bit or 16-bit mode ry/by# ready/busy output v cc 3.0 volt-only single power supply (see product selector guide on page 9 for speed options and voltage supply tolerances) v ss device ground nc pin not connected internally 22 16 or 8 dq15?dq0 (a-1) a21?a0 ce# oe# we# reset# byte# ry/by# wp#/acc
september 8, 2009 s29jl064h_00_a8 s29jl064h 13 data sheet 7. ordering information the order number is formed by a valid combinations of the following: note for new designs involving fine-pitch ball grid array (fbga) packages, s29pl064j supersedes s29jl064h and is the factory recomme nded migration path. please refer to the s29pl-j data sheet for specifications and ordering information. notes 1. listed tsop part numbers describe products based on copper (cu) leadframes. contact your local sales office for products base d on alloy-42 leadframes. 2. type 0 is standard. specify other options as required. 3. tsop package marking omits packing type designator from ordering part number. 4. bga package marking omits leading s29 and packing type designator from ordering part number. s29jl064h 55 t a i 00 0 packing type 0=tray 3 = 13-inch tape and reel model number (additional ordering options) 00 = standard configuration temperature range i = industrial (?40 c to +85 c) package material set a = standard f = pb-free package type t = thin small outline package (tsop) standard pinout b = fine-pitch ball-grid array package (not for new designs - (see note) ) speed option 55 = 55 ns 60 = 60 ns 70 = 70 ns 90 = 90 ns product family s29jl064h: 3.0 volt-only, 64 megabit (4 m x 16-bit/8 m x 8-bit) simultaneous read/write flash memory manufactured on 130 nm process technology s29jl064h valid combinations device family speed option package, material, set and temperature range model number packing type package description s29jl064h 55, 60, 70, 90 tai tfi 00 0, 3 (note 2) ts048 (note 3) tsop bai, bfi fbe063 (note 4) fine-pitch bga
14 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 8. device bus operations this section describes the requiremen ts and use of the device bus operati ons, which are initiated through the internal command register. the command register itse lf does not occupy any add ressable memory location. the register is a latch used to store the commands, along with the addr ess and data information needed to execute the command. the cont ents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 8.1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. legend l = logic low = v il h = logic high = v ih v id = 11.5?12.5 v v hh = 9.0 0.5 v x = don?t care sa = sector address a in = address in d in = data in d out = data out notes: 1. addresses are a21:a0 in word mode (byte# = v ih ), a21:a-1 in byte mode (byte# = v il ). 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see sector/sector block protection and unprotection on page 22 . 3. if wp#/acc = v il , sectors 0, 1, 140, and 141 remain protected. if wp#/acc = v ih , protection on sectors 0, 1, 140, and 141 depends on whether they were last protected or unprotected using the method described in sector/sector block protection and unprotection on page 22 . if wp#/acc = v hh , all sectors will be unprotected. 8.1 word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or wo rd configuration. if the byte# pin is set at logic ?1?, the device is in word c onfiguration, dq15?dq0 are ac tive and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is in byte configuration, and only data i/o pins dq7?dq0 are active and controlled by ce# and oe#. the data i/o pins dq14?dq8 are tri-stated , and the dq15 pin is used as an input for the lsb (a-1) address function. table 8.1 s29jl064h device bus operations operation ce# oe# we# reset# wp#/ acc addresses (note 2) dq15?dq8 dq7? dq0 byte# = v ih byte# = v il read l l h h l/h a in d out dq14?dq8 = high-z, dq15 = a-1 d out write l h l h (note 3) a in d in d in standby v cc 0.3 v xx v cc 0.3 v l/h x high-z high-z high-z output disable l h h h l/h x high-z high-z high-z reset x x x l l/h x high-z high-z high-z sector protect (note 2) lhl v id l/h sa, a6 = l, a1 = h, a0 = l xxd in sector unprotect (note 2) lhl v id (note 3) sa, a6 = h, a1 = h, a0 = l xxd in temporary sector unprotect xxx v id (note 3) a in d in high-z d in
september 8, 2009 s29jl064h_00_a8 s29jl064h 15 data sheet 8.2 requirements for reading array data to read array data from the outputs, the syst em must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output cont rol and gates array data to the output pins. we# should remain at v ih . the byte# pin determines whether the de vice outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory cont ent occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. each bank remains enabled for read access until the command register contents are altered. refer to read-only operations on page 46 for timing specifications and to figure 17.1 on page 46 for the timing diagram. i cc1 in dc characteristics on page 43 represents the active curr ent specification for reading array data. 8.3 writing commands/command sequences to write a command or command sequence (which in cludes programming data to the device and erasing sectors of memory), the syste m must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin determines whet her the device accepts program data in bytes or words. refer to word/byte configuration on page 14 for more information. the device features an unlock bypass mode to facilitate faster progra mming. once a bank enters the unlock bypass mode, only two writ e cycles are required to program a word or byte, instead of four. byte/ word program command sequence on page 32 has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, mu ltiple sectors, or the entire device. table 8.3 on page 20 indicates the address space that eac h sector occupies. similarly, a sector address is the address bits required to uniquely select a sector. command definitions on page 31 has details on erasing a sector or the entire chip, or suspending/r esuming the erase operation. the device address space is divided into four banks. a bank address is the address bits required to uniquely select a bank. i cc2 in the dc characteristics on page 43 represents the active current s pecification for the write mode. ac characteristics on page 46 contains timing specification tables and timing diagrams for write operations. 8.3.1 accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this fu nction is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device automatically enters the aforementioned unlock bypass mode, temporarily unprotects any pr otected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system wo uld use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin returns the device to normal operation. note that v hh must not be asserted on wp#/acc fo r operations other than accelerated programming, or device damage may result. in addi tion, the wp#/acc pin must not be left floating or unconnected; inconsistent behavi or of the device may result . write protect (wp#) on page 23 for related information. 8.3.2 autoselect functions if the system writes the autosele ct command sequence, th e device enters the auto select mode. the system can then read autoselect codes from the internal regi ster (which is separate from the memory array) on dq15?dq0. standard read cycle timings apply in this mode. refer to autoselect mode on page 21 and autoselect command sequence on page 32 for more information.
16 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 8.4 simultaneous read/write operations with zero latency this device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. an erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). figure 17.8 on page 51 shows how read and write cycles may be initiated for simultane ous operation with zero latency. i cc6 and i cc7 in the dc characteristics on page 43 represent the current specificat ions for read-while-p rogram and read-while-erase, respectively. 8.5 standby mode when the system is not reading or writing to the device , it can place the device in the standby mode. in this mode, current consumption is greatl y reduced, and the outputs are plac ed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when t he ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 in dc characteristics on page 43 represents the standby current specification. 8.6 automatic sleep mode the automatic sleep mode minimizes flash device ener gy consumption. the devi ce automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals . standard address access timings pr ovide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc5 in dc characteristics on page 43 represents the automatic sleep mode current specification. 8.7 reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read /write commands for the durat ion of the reset# pulse. the device also resets the internal state machine to reading array data. the oper ation that was interrupted should be reinitiated once the device is ready to acc ept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system rese t would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a progra m or erase operation, the ry/by# pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whet her the reset operation is complete. if reset# is asserted when a program or erase op eration is not executin g (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset# pin returns to v ih . refer to ac characteristics on page 46 for reset# parameters and to figure 17.2 on page 47 for the timing diagram.
september 8, 2009 s29jl064h_00_a8 s29jl064h 17 data sheet 8.8 output disable mode when the oe# input is at v ih , output from the device is disabled. th e output pins are placed in the high impedance state. table 8.2 s29jl064h sector architecture (sheet 1 of 4) bank sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range bank 1 sa0 0000000000 8/4 000000h?001fffh 00000h?00fffh sa1 0000000001 8/4 002000h?003fffh 01000h?01fffh sa2 0000000010 8/4 004000h?005fffh 02000h?02fffh sa3 0000000011 8/4 006000h?007fffh 03000h?03fffh sa4 0000000100 8/4 008000h?009fffh 04000h?04fffh sa5 0000000101 8/4 00a000h?00bfffh 05000h?05fffh sa6 0000000110 8/4 00c000h?00dfffh 06000h?06fffh sa7 0000000111 8/4 00e000h?00ffffh 07000h?07fffh sa8 0000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa9 0000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa10 0000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa11 0000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa12 0000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa13 0000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa14 0000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa15 0001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa16 0001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa17 0001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa18 0001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa19 0001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa20 0001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa21 0001110xxx 64/32 0e0000h?0effffh 70000h?77fffh sa22 0001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh
18 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet bank 2 sa23 0010000xxx 64/32 100000h?10ffffh 80000h?87fffh sa24 0010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa25 0010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa26 0010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa27 0010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa28 0010101xxx 64/32 150000h?15ffffh a8000h?affffh sa29 0010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa30 0010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa31 0011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa32 0011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa33 0011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa34 0011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa35 0011000xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa36 0011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa37 0011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa38 0011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh sa39 0100000xxx 64/32 200000h?20ffffh 100000h?107fffh sa40 0100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa41 0100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa42 0101011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa43 0100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa44 0100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa45 0100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa46 0100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa47 0101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa48 0101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa49 0101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa50 0101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa51 0101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa52 0101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa53 0101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa54 0101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa55 0110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa56 0110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa57 0110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa58 0110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa59 0110100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa60 0110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa61 0110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa62 0110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa63 0111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa64 0111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa65 0111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa66 0111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa67 0111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa68 0111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa69 0111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa70 0111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh table 8.2 s29jl064h sector architecture (sheet 2 of 4) bank sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
september 8, 2009 s29jl064h_00_a8 s29jl064h 19 data sheet bank 3 sa71 1000000xxx 64/32 400000h?40ffffh 200000h?207fffh sa72 1000001xxx 64/32 410000h?41ffffh 208000h?20ffffh sa73 1000010xxx 64/32 420000h?42ffffh 210000h?217fffh sa74 1000011xxx 64/32 430000h?43ffffh 218000h?21ffffh sa75 1000100xxx 64/32 440000h?44ffffh 220000h?227fffh sa76 1000101xxx 64/32 450000h?45ffffh 228000h?22ffffh sa77 1000110xxx 64/32 460000h?46ffffh 230000h?237fffh sa78 1000111xxx 64/32 470000h?47ffffh 238000h?23ffffh sa79 1001000xxx 64/32 480000h?48ffffh 240000h?247fffh sa80 1001001xxx 64/32 490000h?49ffffh 248000h?24ffffh sa81 1001010xxx 64/32 4a0000h?4affffh 250000h?257fffh sa82 1001011xxx 64/32 4b0000h?4bffffh 258000h?25ffffh sa83 1001100xxx 64/32 4c0000h?4cffffh 260000h?267fffh sa84 1001101xxx 64/32 4d0000h?4dffffh 268000h?26ffffh sa85 1001110xxx 64/32 4e0000h?4effffh 270000h?277fffh sa86 1001111xxx 64/32 4f0000h?4fffffh 278000h?27ffffh sa87 1010000xxx 64/32 500000h?50ffffh 280000h?28ffffh sa88 1010001xxx 64/32 510000h?51ffffh 288000h?28ffffh sa89 1010010xxx 64/32 520000h?52ffffh 290000h?297fffh sa90 1010011xxx 64/32 530000h?53ffffh 298000h?29ffffh sa91 1010100xxx 64/32 540000h?54ffffh 2a0000h?2a7fffh sa92 1010101xxx 64/32 550000h?55ffffh 2a8000h?2affffh sa93 1010110xxx 64/32 560000h?56ffffh 2b0000h?2b7fffh sa94 1010111xxx 64/32 570000h?57ffffh 2b8000h?2bffffh sa95 1011000xxx 64/32 580000h?58ffffh 2c0000h?2c7fffh sa96 1011001xxx 64/32 590000h?59ffffh 2c8000h?2cffffh sa97 1011010xxx 64/32 5a0000h?5affffh 2d0000h?2d7fffh sa98 1011011xxx 64/32 5b0000h?5bffffh 2d8000h?2dffffh sa99 1011100xxx 64/32 5c0000h?5cffffh 2e0000h?2e7fffh sa100 1011101xxx 64/32 5d0000h?5dffffh 2e8000h?2effffh sa101 1011110xxx 64/32 5e0000h?5effffh 2f0000h?2fffffh sa102 1011111xxx 64/32 5f0000h?5fffffh 2f8000h?2fffffh sa103 1100000xxx 64/32 600000h?60ffffh 300000h?307fffh sa104 1100001xxx 64/32 610000h?61ffffh 308000h?30ffffh sa105 1100010xxx 64/32 620000h?62ffffh 310000h?317fffh sa106 1100011xxx 64/32 630000h?63ffffh 318000h?31ffffh sa107 1100100xxx 64/32 640000h?64ffffh 320000h?327fffh sa108 1100101xxx 64/32 650000h?65ffffh 328000h?32ffffh sa109 1100110xxx 64/32 660000h?66ffffh 330000h?337fffh sa110 1100111xxx 64/32 670000h?67ffffh 338000h?33ffffh sa111 1101000xxx 64/32 680000h?68ffffh 340000h?347fffh sa112 1101001xxx 64/32 690000h?69ffffh 348000h?34ffffh sa113 1101010xxx 64/32 6a0000h?6affffh 350000h?357fffh sa114 1101011xxx 64/32 6b0000h?6bffffh 358000h?35ffffh sa115 1101100xxx 64/32 6c0000h?6cffffh 360000h?367fffh sa116 1101101xxx 64/32 6d0000h?6dffffh 368000h?36ffffh sa117 1101110xxx 64/32 6e0000h?6effffh 370000h?377fffh sa118 1101111xxx 64/32 6f0000h?6fffffh 378000h?37ffffh table 8.2 s29jl064h sector architecture (sheet 3 of 4) bank sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
20 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet note the address range is a21:a-1 in byte mode (byte# = v il ) or a21:a0 in word mode (byte# = v ih ). bank 4 sa119 1110000xxx 64/32 700000h?70ffffh 380000h?387fffh sa120 1110001xxx 64/32 710000h?71ffffh 388000h?38ffffh sa121 1110010xxx 64/32 720000h?72ffffh 390000h?397fffh sa122 1110011xxx 64/32 730000h?73ffffh 398000h?39ffffh sa123 1110100xxx 64/32 740000h?74ffffh 3a0000h?3a7fffh sa124 1110101xxx 64/32 750000h?75ffffh 3a8000h?3affffh sa125 1110110xxx 64/32 760000h?76ffffh 3b0000h?3b7fffh sa126 1110111xxx 64/32 770000h?77ffffh 3b8000h?3bffffh sa127 1111000xxx 64/32 780000h?78ffffh 3c0000h?3c7fffh sa128 1111001xxx 64/32 790000h?79ffffh 3c8000h?3cffffh sa129 1111010xxx 64/32 7a0000h?7affffh 3d0000h?3d7fffh sa130 1111011xxx 64/32 7b0000h?7bffffh 3d8000h?3dffffh sa131 1111100xxx 64/32 7c0000h?7cffffh 3e0000h?3e7fffh sa132 1111101xxx 64/32 7d0000h?7dffffh 3e8000h?3effffh sa133 1111110xxx 64/32 7e0000h?7effffh 3f0000h?3f7fffh sa134 1111111000 8/4 7f0000h?7f1fffh 3f8000h?3f8fffh sa135 1111111001 8/4 7f2000h?7f3fffh 3f9000h?3f9fffh sa136 1111111010 8/4 7f4000h?7f5fffh 3fa000h?3fafffh sa137 1111111011 8/4 7f6000h?7f7fffh 3fb000h?3fbfffh sa138 1111111100 8/4 7f8000h?7f9fffh 3fc000h?3fcfffh sa139 1111111101 8/4 7fa000h?7fbfffh 3fd000h?3fdfffh sa140 1111111110 8/4 7fc000h?7fdfffh 3fe000h?3fefffh sa141 1111111111 8/4 7fe000h?7fffffh 3ff000h?3fffffh table 8.3 bank address bank a21?a19 1 000 2 001, 010, 011 3 100, 101, 110 4 111 table 8.4 secured silicon sector addresses device sector size (x8) address range (x16) address range s29jl064h 256 bytes 000000h?0000ffh 000000h?00007fh table 8.2 s29jl064h sector architecture (sheet 4 of 4) bank sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
september 8, 2009 s29jl064h_00_a8 s29jl064h 21 data sheet 8.9 autoselect mode the autoselect mode provides manufa cturer and device identification, an d sector protection verification, through identifier codes output on dq7?dq0. this mo de is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through th e command register. when using programming equipment, the autoselect mode requires v id on address pin a9. address pins must be as shown in table 8.5 . in addition, when verifying sector pr otection, the sector address must appear on the appropriate highest order address bits (see table 8.3 on page 20 ). table 8.5 shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifi er code on dq7?dq0. however, the autoselect codes can also be accessed in-system through the command register, for instances when the s29jl064 is erased or programmed in a system without access to high vo ltage on the a9 pin. the command sequence is illustrated in table 10.1 on page 36 . note that if a bank address (ba) on address bits a21, a20, and a19 is asserted during the thir d write cycle of the autosel ect command, the host system can read autoselect data from that bank and then immediat ely read array data from another bank , without exiting the autoselect mode. to access the autoselect codes in-system, the hos t system can issue the aut oselect command via the command register, as shown in table 10.1 on page 36 . this method does not require v id . refer to autoselect command sequence on page 32 for more information. legend l = logic low = v il h = logic high = v ih ba = bank address sa = sector address x = don?t care. table 8.5 s29jl064h autoselect codes, (high voltage method) description ce# oe# we# a21 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a4 a3 a2 a1 a0 dq15 to dq8 dq7 to dq0 byte# = v ih byte# = v il manufacturer id : spansion products llhbaxv id xlxllll x x 01h device id read cycle 1 llhbaxv id x l x lllh 22h x 7eh read cycle 2 l h h h l 22h 02h read cycle 3 l h h h h 22h 01h sector protection verification llhsaxv id xlxllhl x x 01h (protected), 00h (unprotected) secured silicon indicator bit (dq6, dq7) llhbaxv id xlxllhh x x 81h (factory locked), 01h (not factory/ customer locked)
22 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 8.10 sector/sector block pr otection and unprotection (note: for the following discussion, the term sector applies to both sectors and se ctor blocks. a sector block consists of two or more adjacent sectors that are protected or u nprotected at the same time (see table 8.6 ). the hardware sector protection feature disables bot h program and erase operations in any sector. the hardware sector unprotection featur e re-enables both program and erase ope rations in previously protected sectors. sector protection/unprotection can be implemented via two methods. table 8.6 s29jl064h boot sector/sector block addresses for protection/unprotection (sheet 1 of 2) sector a21?a12 sector/sector block size sa0 0000000000 8 kbytes sa1 0000000001 8 kbytes sa2 0000000010 8 kbytes sa3 0000000011 8 kbytes sa4 0000000100 8 kbytes sa5 0000000101 8 kbytes sa6 0000000110 8 kbytes sa7 0000000111 8 kbytes sa8?sa10 0000001xxx, 0000010xxx, 0000011xxx, 192 (3x64) kbytes sa11?sa14 00001xxxxx 256 (4x64) kbytes sa15?sa18 00010xxxxx 256 (4x64) kbytes sa19?sa22 00011xxxxx 256 (4x64) kbytes sa23?sa26 00100xxxxx 256 (4x64) kbytes sa27-sa30 00101xxxxx 256 (4x64) kbytes sa31-sa34 00110xxxxx 256 (4x64) kbytes sa35-sa38 00111xxxxx 256 (4x64) kbytes sa39-sa42 01000xxxxx 256 (4x64) kbytes sa43-sa46 01001xxxxx 256 (4x64) kbytes sa47-sa50 01010xxxxx 256 (4x64) kbytes sa51-sa54 01011xxxxx 256 (4x64) kbytes sa55?sa58 01100xxxxx 256 (4x64) kbytes sa59?sa62 01101xxxxx 256 (4x64) kbytes sa63?sa66 01110xxxxx 256 (4x64) kbytes sa67?sa70 01111xxxxx 256 (4x64) kbytes sa71?sa74 10000xxxxx 256 (4x64) kbytes sa75?sa78 10001xxxxx 256 (4x64) kbytes sa79?sa82 10010xxxxx 256 (4x64) kbytes sa83?sa86 10011xxxxx 256 (4x64) kbytes sa87?sa90 10100xxxxx 256 (4x64) kbytes sa91?sa94 10101xxxxx 256 (4x64) kbytes sa95?sa98 10110xxxxx 256 (4x64) kbytes sa99?sa102 10111xxxxx 256 (4x64) kbytes sa103?sa106 11000xxxxx 256 (4x64) kbytes sa107?sa110 11001xxxxx 256 (4x64) kbytes sa111?sa114 11010xxxxx 256 (4x64) kbytes sa115?sa118 11011xxxxx 256 (4x64) kbytes sa119?sa122 11100xxxxx 256 (4x64) kbytes sa123?sa126 11101xxxxx 256 (4x64) kbytes sa127?sa130 11110xxxxx 256 (4x64) kbytes
september 8, 2009 s29jl064h_00_a8 s29jl064h 23 data sheet sector protect/sector unprotect requires v id on the reset# pin only, and c an be implemented either in- system or via programming equipment. figure 8.2 on page 25 shows the algorithms and figure 17.13 on page 54 shows the timing diagram. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. note that the sector unprotect algorithm unprotects all sectors in parallel. all previously protected sect ors must be individually re-protected. to change data in protected sectors efficiently, the te mporary sector unprotect function is available. see temporary sector unprotect on page 53 . the device is shipped with all sectors unprotect ed. optional spansion programming service enable programming and protecting sectors at the factory prior to shipping the device. contact your local sales office for details. it is possible to determine whether a se ctor is protected or unprotected. see autoselect mode on page 21 for details. 8.11 write protect (wp#) the write protect function provides a hardw are method of protecting without using v id . this function is one of two provided by the wp#/acc pin. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in sectors 0, 1, 140, and 141, independently of whether those sector s were protected or unprotected using the method described in sector/sector block prot ection and unprotection on page 22 . if the system asserts v ih on the wp#/acc pin, the device reverts to whether sectors 0, 1, 140, and 141 were last set to be protected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or un protected using the method described in sector/sector block protection and unprotection on page 22 . note that the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. sa131?sa133 1111100xxx, 1111101xxx, 1111110xxx 192 (3x64) kbytes sa134 1111111000 8 kbytes sa135 1111111001 8 kbytes sa136 1111111010 8 kbytes sa137 1111111011 8 kbytes sa138 1111111100 8 kbytes sa139 1111111101 8 kbytes sa140 1111111110 8 kbytes sa141 1111111111 8 kbytes table 8.6 s29jl064h boot sector/sector block addresses for protection/unprotection (sheet 2 of 2) sector a21?a12 sector/sector block size table 8.7 wp#/acc modes wp# input voltage device mode v il disables programming and erasing in sa0, sa1, sa140, and sa141 v ih enables programming and erasing in sa0, sa1, sa140, and sa141, dependent on whether they were last protected or unprotected. v hh enables accelerated programming (acc). see accelerated program operation on page 15.
24 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 8.12 temporary sector unprotect (note: for the following discussion, the term sector applies to both sectors and se ctor blocks. a sector block consists of two or more adjacent sectors that are protected or u nprotected at the same time (see table 8.6 on page 22 ). this feature allows temporary unprotection of previo usly protected sectors to change data in-system. the temporary sector unprotect mode is ac tivated by setting the reset# pin to v id . during this mode, formerly protected sectors can be programmed or erased by selecting the sect or addresses. once v id is removed from the reset# pin, all th e previously protected se ctors are protected again. figure 8.1 shows the algorithm, and figure 17.12 on page 53 shows the timing diagrams, for this feature. if the wp#/acc pin is at v il , sectors 0, 1, 140, and 141 will remain protec ted during the temporary sector unprotect mode. figure 8.1 temporary sector unprotect operation notes 1. all protected sectors unprotected (if wp#/acc = v il , sectors 0, 1, 140, and 141 will remain protected). 2. all previously protected sectors are protected once again. start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1)
september 8, 2009 s29jl064h_00_a8 s29jl064h 25 data sheet figure 8.2 in-system sector protec t/unprotect algorithms sector protect: write 60h to sector address with a6=0, a3=0, a2=0, a1=1, a0=0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6=0, a3=0, a2=0, a1=1, a0=0 read from sector address with a6=0, a3=0, a2=0, a1=1, a0=0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6=1, a3=0, a2=0, a1=1, a0=0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6=1, a3=0, a2=0, a1=1, a0=0 read from sector address with a6=1, a3=0, a2=0, a1=1, a0=0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
26 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 8.13 secured silicon sect or flash memory region the secured silicon sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secured silicon sector is 256 bytes in length, and uses a secured silicon sector indicator bit (dq7) to indicate whether or not the secured silicon sector is locked when shipped from the factory. this bit is pe rmanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ens ures the security of the esn once the product is shipped to the field. the product is available with the secured silicon sect or either factory locked or customer lockable. the factory-locked version is always protected when shipped from the factory, and has the secured silicon sector indicator bit permanently set to a 1 . the customer-lockable version is shipped with the secured silicon sector unprotected, allowing customer s to utilize the that sector in an y manner they choose. the customer- lockable version has the secured silicon sector indicator bit permanently set to a 0 . thus, the secured silicon sector indicator bit prevents customer-lockabl e devices from being used to replace devices that are factory locked. the system accesses the secured silicon sector through a command sequence (see enter secured silicon sector/exit secured silicon sector command sequence on page 32 ). after the system ha s written the enter secured silicon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by the boot sectors. this mode of operation continues until t he system issues the exit secured silicon sector command sequence, or until pow er is removed from the device. on power-up, or following a hardware reset, the device reverts to s ending commands to the first 256 bytes of sector 0. note that the acc function and unlock bypass modes are not available when the secured silicon sector is enabled. 8.13.1 factory locked: secur ed silicon sector program med and protected at the factory in a factory locked device, the secured silicon sector is protected when the device is shipped from the factory. the secured silicon sector cannot be modified in any way. the device is preprogrammed with both a random number and a secure esn. the 8-word ra ndom number is at addresses 000000h?000007h in word mode (or 000000h?00000fh in byte mode). the secure esn is programmed in the next 8 words at addresses 000008h?00000fh (or 000010h?00001fh in byte mode). the device is available preprogrammed with one of the following: ? a random, secure esn only ? customer code through spansion programming services ? both a random, secure esn and customer code through spansion programming services contact an your local sales office for detai ls on using spansion programming services. 8.13.2 customer lockable: se cured silicon sector not programmed or protected at the factory if the security feature is not required, the secured silicon sector can be treated as an additional flash memory space. the secured silicon sector can be read any number of times, but can be programmed and locked only once. note that the accelerated prog ramming (acc) and unlock bypass functions are not available when programming the secured silicon sector. the secured silicon sector area can be prot ected using one of the following procedures: ? write the three-cycle enter secured silicon sector region command sequence, and then follow the in- system sector protect al gorithm as shown in figure 8.2 on page 25 , except that reset# may be at either v ih or v id . this allows in-system protection of the secured silicon sector r egion without raising any device pin to a high voltage. note that this method is only applicable to the secured silicon sector. ? to verify the protect/unprotect status of the secured silicon sector, follow the algorithm shown in figure 8.3 on page 27 . once the secured silicon sector is locked and verified, the system must wr ite the exit secured silicon sector region command sequence to return to reading and writing the remainder of the array.
september 8, 2009 s29jl064h_00_a8 s29jl064h 27 data sheet the secured silicon sector lock must be used with caution since, once locked, there is no procedure available for unlocking the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way. figure 8.3 secured silicon sector protect verify 8.14 hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 10.1 on page 36 for command definitions). in addition, the following hardware data protection measures prevent accidental erasure or pr ogramming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down tran sitions, or from system noise. 8.14.1 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the cont rol pins to prevent uni ntentional writes when v cc is greater than v lko . 8.14.2 write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce# or we # do not initiate a write cycle. 8.14.3 logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. 8.14.4 power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is aut omatically reset to the read mode on power-up. write 60h to a ny a ddre ss write 40h to s ec u re s ilicon s ector a ddre ss with a6 = 0, a1 = 1, a0 = 0 s ta rt re s et# = v ih or v id w a it 1 m s re a d from s ec u re s ilicon s ector a ddre ss with a6 = 0, a1 = 1, a0 = 0 if d a t a = 00h, s ec u re s ilicon s ector i s u nprotected. if d a t a = 01h, s ec u re s ilicon s ector i s protected. remove v ih or v id from re s et# write re s et comm a nd s ec u re s ilicon s ector protect verify complete
28 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 9. common flash memory interface (cfi) the common flash in terface (cfi) specification outlines device and host system software in terrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device -independent, jedec id-independent, and forward- and backward-compatible for the specifie d flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in table 9.1 on page 28 to table 9.4 on page 30 . to terminate reading cfi data, the syste m must write the reset command.the cfi query mode is not accessible when the device is executing an embedded program or embedded erase algorithm. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in table 9.1 on page 28 to table 9.4 on page 30 . the system must write the reset command to reading array data. for further information, please refer to the cfi specificat ion and cfi publication 100. contact your local sales office for copies of these documents. table 9.1 cfi query identification string addresses (word mode) addresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) table 9.2 system interface string addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0003h typical timeout per single byte/word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 0009h typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
september 8, 2009 s29jl064h_00_a8 s29jl064h 29 data sheet table 9.3 device geometry definition addresses (word mode) addresses (byte mode) data description 27h 4eh 0017h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0003h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specificat ion or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 007dh 0000h 0000h 0001h erase block region 2 information (refer to the cfi specificat ion or cfi publication 100) 35h 36h 37h 38h 6ah 6ch 6eh 70h 0007h 0000h 0020h 0000h erase block region 3 information (refer to the cfi specificat ion or cfi publication 100) 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specificat ion or cfi publication 100)
30 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet table 9.4 primary vendor-specific extended query addresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii (reflects modifications to the silicon) 44h 88h 0033h minor version number, ascii (reflects modifications to the cfi table) 45h 8ah 000ch address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 01 =29f040 mode, 02 = 29f016 mode, 03 = 29f400, 04 = 29lv800 mode 4ah 94h 0077h simultaneous operation 00 = not supported, x = number of sectors (excluding bank 1) 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 0001h top/bottom boot sector flag 00h = uniform device, 01h = 8 x 8 kbyte sectors, top and bottom boot with write protect, 02h = bottom boot device, 03h = top boot device, 04h= both top and bottom 50h a0h 0001h program suspend 0 = not supported, 1 = supported 57h aeh 0004h bank organization 00 = data at 4ah is zero, x = number of banks 58h b0h 0017h bank 1 region information x = number of sectors in bank 1 59h b2h 0030h bank 2 region information x = number of sectors in bank 2 5ah b4h 0030h bank 3 region information x = number of sectors in bank 3 5bh b6h 0017h bank 4 region information x = number of sectors in bank 4
september 8, 2009 s29jl064h_00_a8 s29jl064h 31 data sheet 10. command definitions writing specific address and data co mmands or sequences into the co mmand register initiates device operations. table 10.1 on page 36 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequenc e may place the device in an unknown state. a reset command is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to ac characteristics on page 46 for timing diagrams. 10.1 reading array data the device is automatically set to reading array data af ter device power-up. no commands are required to retrieve data. each bank is ready to read array da ta after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-suspend- read mode, after which the system can read data fr om any non-erase-suspended sector within the same bank. the system can read array data using the standard read timing, exce pt that if it reads at an address within erase-suspended sectors, the devi ce outputs status data. after comp leting a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see erase suspend/erase resume commands on page 35 for more information. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. see reset command on page 31 for more information. see requirements for reading array data on page 15 for more information. read-only operations on page 46 provides the read parameters, and figure 17.1 on page 46 shows the timing diagram. 10.2 reset command writing the reset command resets the banks to the read or erase-suspend-read mode . address bits are don?t cares for this command. the reset command may be written between the s equence cycles in an erase command sequence before erasing begins. this resets the bank to which the syst em was writing to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be writt en between the s equence cycles in a progra m command sequence before programming begins. this resets the bank to which t he system was writing to the read mode. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-su spend-read mode. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequ ence cycles in an autose lect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase susp end mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend).
32 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 10.3 autoselect command sequence the autoselect command sequence allows the host sys tem to access the manufacturer and device codes, and determine whether or not a sector is protected. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively programming or erasing in another bank. the autoselect command sequence is in itiated by first writing two unlock c ycles. this is followed by a third write cycle that contains the bank address and the autos elect command. the bank then enters the autoselect mode. the system may read any num ber of autoselect codes without re -initiating the command sequence. table 10.1 on page 36 shows the address and data requirem ents. to determine sector protection information, the system must write to the appropriate ban k address (ba) and sector address (sa). table 8.3 on page 20 shows the address range and bank number associated with each sector. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend). 10.4 enter secured silicon sector/exi t secured silicon sector command sequence the secured silicon sector region provides a secured data area containing a random , sixteen-byte electronic serial number (esn). the system can access the secured silicon sector region by issu ing the three-cycle enter secured silicon sector command sequence. t he device continues to a ccess the secured silicon sector region until the system issues the four-cycle exit secured silicon sector co mmand sequence. the exit secured silicon sector command sequence returns t he device to normal operation. the secured silicon sector is not accessible when the device is executing an embedded pr ogram or embedded erase algorithm. table 10.1 on page 36 shows the address and data requirements for both command sequences. see also secured silicon sector flash memory region on page 26 for further information. note that the acc function and unlock bypass modes are not available when the secured silicon sector is enabled. 10.5 byte/word program command sequence the system may program the device by word or byte, depending on the state of the byte# pin. programming is a four-bus-cycle operation. the program command sequen ce is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generat ed program pulses and verifies the programmed cell margin. table 10.1 on page 36 shows the address and data requirem ents for the byte program command sequence. when the embedded program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by using dq7, dq6, or ry/by#. refer to write operation status on page 37 for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program operat ion. the program command sequence should be reinitiated once that bank has returned to th e read mode, to ensure data integrity. note that the secured silicon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from 0 back to a 1 . attempting to do so may cause that bank to se t dq5 = 1, or cause t he dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still 0. only erase operations can convert a 0 to a 1 .
september 8, 2009 s29jl064h_00_a8 s29jl064h 33 data sheet 10.5.1 unlock bypa ss command sequence the unlock bypass feature allows the system to program bytes or words to a bank faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypa ss command, 20h. that bank then enters the unl ock bypass mode. a two-cycle unlock bypass progr am command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initia l two unlock cycles required in the standard program command sequence, resulting in faster total programming time. table 10.1 on page 36 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (see table 10.1 on page 36 ). the device offers accelerated program operations th rough the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the de vice automatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequen ce. the device uses the higher voltage on the wp#/ acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh for any operation other than accelerated programming, or device damage may re sult. in addition, the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result . figure 10.1 on page 33 illustrates the algorithm for the program operation. refer to erase and program operations on page 49 for parameters, and figure 17.5 on page 50 for timing diagrams. figure 10.1 program operation note 1. see table 10.1 on page 36 for program command sequence. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
34 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 10.6 chip erase command sequence chip erase is a six bus cycle operatio n. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlo ck write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the emb edded erase algorithm automatically pr eprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings du ring these operations. table 10.1 on page 36 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system can determi ne the status of the er ase operation by using dq 7, dq6, dq2, or ry/ by#. refer to write operation status on page 37 for information on these status bits. any commands written during the chip erase op eration are ignored. however, note that a hardware reset immediately terminates the erase operation. if that o ccurs, the chip erase command sequence should be reinitiated once that bank has returned to read ing array data, to ens ure data integrity. note that the secured silicon sector, autoselect, and cfi functions are unav ailable when an erase operation is in progress. figure 10.2 on page 35 illustrates the algorithm for the erase operation. refer to erase and program operations on page 49 for parameters, and figure 17.7 on page 51 for timing diagrams. 10.7 sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. table 10.1 on page 36 shows the address and data requirements for t he sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies the entire sector for an all zero data pattern prior to electrical erase. the system is not required to provide any cont rols or timings during these operations. after the command sequence is written, a sector erase time-out of 80 s occurs. during the time-out period, additional sector addresses and sector erase commands ma y be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be le ss than 80 s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may no t be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sect or erase command is written. any command other than sector erase or erase suspend duri ng the time-out peri od resets that bank to the read mode. the system must rewrite the command sequence and any additional addresses and commands. the system can monitor dq3 to determ ine if the sector erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ri sing edge of the final we# or ce# pulse (first rising edge) in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can determine the status of the erase oper ation by reading dq7, dq6, dq2, or ry/by# in the erasing bank. refer to write operation status on page 37 for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operat ion. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. note that the secured silicon sector, autoselect, and cfi functions are unavailable when an erase operation is in progress. figure 10.2 on page 35 illustrates the algorithm for the erase operation. refer to erase and program operations on page 49 for parameters, and figure 17.7 on page 51 for timing diagrams.
september 8, 2009 s29jl064h_00_a8 s29jl064h 35 data sheet figure 10.2 erase operation notes 1. see table 10.1 on page 36 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer. 10.8 erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector eras e operation and then read data from, or program data to, any se ctor not selected for er asure. the bank address is required when writing this command. this command is valid only during the se ctor erase operation, including the 80 s time-out period during the sector er ase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm . the bank address must contain one of the sectors currently selected for erase. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediatel y terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the ba nk enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) reading at any addre ss within erase-suspended se ctors produces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to write operation status on page 37 for information on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq 7 or dq6 status bits, just as in the standard byte program operation. refer to write operation status on page 37 for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. the device allows reading autoselect codes even at addresses within erasing sectors, since t he codes are not stored in the memory array. when the device exits the autos elect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. refer to autoselect mode on page 21 and autoselect command sequence on page 32 for details. to resume the sector erase operation, the syst em must write the erase resume command. the bank address of the erase-suspended bank is required when wr iting this command. furthe r writes of the resume command are ignored. another erase su spend command can be written afte r the chip has resumed erasing. start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress
36 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet legend x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever ha ppens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a21?a12 uniquely select any sector. refe r to table 8.3 on page 20 for information on sector addresses. ba = address of the bank that is being swit ched to autoselect mode, is in bypass mode, or is being erased. a21?a19 uniquely sel ect a bank. notes 1. see table 8.1 on page 14 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth, fifth, and sixth c ycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a21?a11 are don?t cares for unlock and command cycles, unless sa or pa is required. 6. no unlock or command cycles required when bank is reading array data. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) w hen a bank is in the autoselect mode, or if dq5 goes high (while the ba nk is providing status information). 8. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address to obtain the m anufacturer id, device id, or secured silicon sector factory protect information. data bits dq15?dq8 are don?t care. while reading the autoselect addresses, the bank address must be the same until a reset command is given. see autoselect command sequence on page 32 for more information. 9. the device id must be read across the fourth, fifth, and sixth cycles. 10. the data is 81h for factory locked, 41h for customer locked, and 01h for not factory/customer locked. table 10.1 s29jl064h command definitions command sequence (note 1) cycles bus cycles (notes 2 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1ra rd reset (note 7) 1xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 (ba)555 90 (ba)x00 01 byte aaa 555 (ba)aaa device id (note 9) word 6 555 aa 2aa 55 (ba)555 90 (ba)x01 7e (ba)x0e 02 (ba)x0f 01 byte aaa 555 (ba)aaa (ba)x02 (ba)x1c (ba)x1e secured silicon sector factory protect (note 10) word 4 555 aa 2aa 55 (ba)555 90 (ba)x03 81/01 byte aaa 555 (ba)aaa (ba)x06 sector/sector block protect verify (note 11) word 4 555 aa 2aa 55 (ba)555 90 (sa)x02 00/01 byte aaa 555 (ba)aaa (sa)x04 enter secured silicon sector region word 3 555 aa 2aa 55 555 88 byte aaa 555 aaa exit secured silicon sector region word 4 555 aa 2aa 55 555 90 xxx 00 byte aaa 555 aaa program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 12) 2 xxx a0 pa pd unlock bypass reset (note 13) 2xxx 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 14) 1ba b0 erase resume (note 15) 1ba 30 cfi query (note 15) word 1 55 98 byte aa
september 8, 2009 s29jl064h_00_a8 s29jl064h 37 data sheet 11. the data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 12. the unlock bypass command is required pr ior to the unlock bypass program command. 13. the unlock bypass reset command is required to return to the read mode when the bank is in the unlock bypass mode. 14. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the er ase suspend command is valid only during a sector erase operation, and requires the bank address. 15. the erase resume command is valid only during the erase suspend mode, and requires the bank address. command is valid when d evice is ready to read array data or when device is in autoselect mode. 11. write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 11.1 on page 42 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. 11.1 dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the devic e outputs on dq7 the co mplement of the datum programmed to dq7. this dq7 status also appl ies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for app roximately 1 s, then that bank returns to the read mode. during the embedded erase algori thm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a 1 on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all se ctors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the bank returns to the read mode. if not all selected sectors are protected, the embedde d erase algorithm erases the unprotect ed sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a pr otected sector, the status may not be valid. when the system detects dq7 has c hanged from the complement to tr ue data, it can read valid data at dq15?dq0 (or dq7?dq0 for x8-only device) on the following read cycles. just prior to the completion of an embedded program or erase operation, dq7 may chang e asynchronously with dq15?dq8 (dq7?dq0 for x8-only device) while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq15?dq0 ma y be still invalid. valid data on dq15?dq0 (or dq7?dq0 for x8-only device) will appear on successive read cycles. table 11.1 on page 42 shows the outputs for data# polling on dq7. figure 11.1 on page 38 shows the data# polling algorithm. figure 17.9 on page 52 shows the data# polling timing diagram.
38 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet figure 11.1 data# polling algorithm notes 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 11.2 ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin wh ich indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-dra in output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the devic e is actively erasing or programmi ng. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. table 11.1 on page 42 shows the outputs for ry/by#. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
september 8, 2009 s29jl064h_00_a8 s29jl064h 39 data sheet 11.3 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the se ctor erase time-out. during an embedded program or erase algorithm operatio n, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce # to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sect ors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all se lected sectors are protected, the embedded erase algorithm erases the unprotected sect ors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 toget her to determine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq 6 stops toggling. howe ver, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternativ ely, the system can use dq7 (see dq7: data# polling on page 37 ). if a program address falls within a protected sector, dq6 toggles for approximatel y 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete.
40 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet figure 11.2 toggle bit algorithm note the system should recheck the toggle bit even if dq5 = 1 because the toggle bit may st op toggling as dq5 changes to 1 . see the subsections on dq6 and dq2 for more information. 11.4 dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have be en selected for erasure. (the system may use either oe# or ce# to control t he read cycles.) but dq2 cann ot distinguis h whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indica tes whether the device is actively erasing, or is in erase su spend, but cannot distingu ish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 11.1 on page 42 to compare outputs for dq2 and dq6. figure 11.2 on page 40 shows the toggle bit algorithm in flowchart form, and dq2: toggle bit ii on page 40 explains the algorithm. see also dq6: toggle bit i on page 39 . figure 17.10 on page 52 shows the toggle bit timing diagram. figure 17.11 on page 53 shows the differences between dq2 and dq6 in graphical form. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete toggle bit = toggle? read byte twice (dq7?dq0) address = va read byte (dq7?dq0) address =va read byte (dq7?dq0) address =va
september 8, 2009 s29jl064h_00_a8 s29jl064h 41 data sheet 11.5 reading toggle bits dq6/dq2 refer to figure 11.2 on page 40 for the following discussi on. whenever the system in itially begins reading toggle bit status, it must read dq15?dq0 (or dq7?dq 0 for x8-only device) at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and stor e the value of the toggle bit after the first read. after the second read, the syst em would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq15?d q0 (or dq7?dq0 for x8-only device) on the following read cycle. however, if after the initial two re ad cycles, the system determi nes that the toggle bit is still to ggling, the system also should note whet her the value of dq5 is high (see the section on dq5) . if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successf ully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 11.2 on page 40 ). 11.6 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1 , indicating that th e program or erase cycle was not successfully completed. the device may output a 1 on dq5 if the system tries to program a 1 to a location that was previously programmed to 0 . only an erase operation can change a 0 back to a 1 . under this condition, the device halts the operation, and when the timing limit has been exceede d, dq5 produces a 1 . under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previ ously in the erase-suspend-program mode). 11.7 dq3: sector erase timer after writing a sector erase comm and sequence, the system may read dq 3 to determ ine whether or not erasure has begun. (the sector erase ti mer does not apply to the chip eras e command.) if additional sectors are selected for erasure, the entire time-out also ap plies after each additional sector erase command. when the time-out period is comp lete, dq3 switches from a 0 to a 1 . if the time between additional sector erase commands from the system can be assumed to be le ss than 50 s, the system need not monitor dq3. see also sector erase command sequence on page 34 . after the sector erase command is wr itten, the system should re ad the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is 1 , the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is 0 , the device will accept additiona l sector erase commands. to ensure the command has been accepted, the system softwa re should check the status of dq3 prior to and following each subsequent sector erase command. if dq 3 is high on the second status check, the last command might not have been accepted. table 11.1 on page 42 shows the status of dq3 relati ve to the other status bits.
42 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet notes 1. dq5 switches to 1 when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addresses a non-busy bank. 12. absolute maximum ratings notes 1. minimum dc voltage on input or i/o pins is ?0.5 v. duri ng voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 12.1 on page 42 . during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 12.2 on page 42 . 2. minimum dc input voltage on pins a9, oe#, reset#, and wp#/acc is ?0.5 v. during voltage transitions, a9, oe#, wp#/acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 12.1 on page 42 . maximum dc input voltage on pin a9 is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. maximum dc input voltage on wp#/acc is +9.5 v which may oversho ot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. this is a stress ratin g only; functional operation of the device at these or any other conditio ns above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 12.1 maximum negative overshoot waveform figure 12.2 maximum positive overshoot waveform table 11.1 write operation status status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode erase-suspend-read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0 storage temperature, plastic packages ?65c to +150c ambient temperature with power applied ?65c to +125c voltage with respect to ground v cc (note 1) ?0.5 v to +4.0 v a9 , oe# , and reset# (note 2) ?0.5 v to +12.5 v wp#/acc ?0.5 v to +10.5 v all other pins (note 1) ?0.5 v to v cc +0.5 v output short circuit current (note 3) 200 ma 20 ns 20 ns +0. 8 v ?0.5 v 20 ns ?2.0 v 20 n s 20 ns v cc +2. 0 v v cc +0. 5 v 20 ns 2.0 v
september 8, 2009 s29jl064h_00_a8 s29jl064h 43 data sheet 13. operating ranges industrial (i) devices ambient temperature (t a ) ?40c to +85c v cc supply voltages v cc for standard voltage range 2.7 v to 3.6 v operating ranges define those limits between whic h the functionality of th e device is guaranteed. 14. dc characteristics 14.1 cmos compatible notes 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 5. not 100% tested. parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, oe# and reset# input load current v cc = v cc max , oe# = v ih ; a9 or oe# or reset# = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max , oe# = v ih 1.0 a i lr reset leakage current v cc = v cc max ; reset# = 12.5 v 35 a i cc1 v cc active read current (notes 1 , 2 ) ce# = v il , oe# = v ih , byte mode 5 mhz 10 16 ma 1 mhz 2 4 ce# = v il , oe# = v ih , word mode 5 mhz 10 16 1 mhz 2 4 i cc2 v cc active write current (notes 2 , 3 )ce# = v il , oe# = v ih , we# = v il 15 30 ma i cc3 v cc standby current (note 2) ce#, reset# = v cc 0.3 v 0.2 5 a i cc4 v cc reset current (note 2) reset# = v ss 0.3 v 0.2 5 a i cc5 automatic sleep mode (notes 2 , 4 ) v ih = v cc 0.3 v; v il = v ss 0.3 v 0.2 5 a i cc6 v cc active read-while-program current (notes 1 , 2 )ce# = v il , oe# = v ih byte 21 45 ma word 21 45 i cc7 v cc active read-while-erase current (notes 1 , 2 )ce# = v il , oe# = v ih byte 21 45 ma word 21 45 i cc8 v cc active program-while-erase-suspended current (notes 2 , 5 ) ce# = v il , oe# = v ih 17 35 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v v hh voltage for wp#/acc sector protect/unprotect and program acceleration v cc = 3.0 v 10% 8.5 9.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0 v 10% 11.5 12.5 v v ol output low voltage i ol = 2.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = ?100 a, v cc = v cc min v cc ?0.4 v lko low v cc lock-out voltage (note 5) 1.8 2.0 2.3 v
44 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 14.2 zero-power flash figure 14.1 i cc1 current vs. time (showing active and automatic sleep currents) note addresses are switching at 1 mhz figure 14.2 typical i cc1 vs. frequency note t = 25 c 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 10 8 2 0 1 2345 frequency in mhz supply current in ma 2.7 v 3.6 v 4 6 12
september 8, 2009 s29jl064h_00_a8 s29jl064h 45 data sheet 15. test conditions figure 15.1 test setup note diodes are in3064 or equivalent 16. key to switching waveforms figure 16.1 input waveforms and measurement levels table 15.1 test specifications test condition 55, 60 70, 90 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v 2.7 k c l 6.2 k 3.3 v device under te s t waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input
46 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 17. ac characteristics 17.1 read-only operations notes 1. not 100% tested. 2. see figure 15.1 on page 45 and table 15.1 on page 45 for test specifications 3. measurements performed by placing a 50 ohm termination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df . figure 17.1 read operation timings parameter description test setup speed options jedec std. 55 60 70 90 unit t avav t rc read cycle time (note 1) min55607090ns t avqv t acc address to output delay ce#, oe# = v il max55607090ns t elqv t ce chip enable to output delay oe# = v il max55607090ns t glqv t oe output enable to output delay max 25 30 35 ns t ehqz t df chip enable to output high z (notes 1 , 3 ) max 16 ns t ghqz t df output enable to output high z (notes 1 , 3 ) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 5 10 ns t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df
september 8, 2009 s29jl064h_00_a8 s29jl064h 47 data sheet 17.2 hardware reset (reset#) note not 100% tested. figure 17.2 reset timings parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb
48 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 17.3 word/byte configuration (byte#) figure 17.3 byte# timings for read operations figure 17.4 byte# timings for write operations note refer to the erase/program operations table for t as and t ah specifications. parameter description speed options unit jedec std. 55607090 t elfl/ t elfh ce# to byte# switching low or high max 5 ns t flqz byte# switching low to output high z max 16 ns t fhqv byte# switching high to output active max 55 60 70 90 ns dq15 output data output ce# oe# byte# t elfl dq14?dq0 data output (dq14?dq0) dq15/a-1 address input t flqz byte# switching from word to byte dq15 output data byte# t elfh dq14?dq0 data output (dq14?dq0) dq15/a-1 address input t fhqv byte# switching from byte to word mode ce# we# byte# the falling edge of the last we# signal t hold (t ah ) t set (t as )
september 8, 2009 s29jl064h_00_a8 s29jl064h 49 data sheet 17.4 erase and program operations notes 1. not 100% tested. 2. see erase and programming performance on page 56 for more information. parameter description speed options unit jedec std 55 60 70 90 t avav t wc write cycle time (note 1) min55607090ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min30354045ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min30354045ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 25 25 30 35 ns t whdl t wph write pulse width high min 25 25 30 30 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) byte typ 5 s word typ 7 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) ty p 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.4 sec t vcs v cc setup time (note 1) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns
50 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet figure 17.5 program operation timings notes 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows de vice in word mode. figure 17.6 accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa wp#/acc t vhh v hh v il or v ih v il or v ih t vhh
september 8, 2009 s29jl064h_00_a8 s29jl064h 51 data sheet figure 17.7 chip/sector erase operation timings notes 1. sa = sector address (for sector erase), va = valid address for reading status data (see write operation status on page 37 . 2. these waveforms are for the word mode. figure 17.8 back-to-back read/write cycle timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t rc t ce valid out t oe t acc t oeh t ghwl t df valid in ce# or ce2# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w
52 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet figure 17.9 data# polling timings (during embedded algorithms) note va = valid address. illustration shows first status cycle afte r command sequence, last status read cycle, and array data read c ycle figure 17.10 toggle bit timings (during embedded algorithms) note va = valid address; not required for dq6. illustration shows fi rst two status cycle after command sequence, last status read cy cle, and array data read cycle. we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by#
september 8, 2009 s29jl064h_00_a8 s29jl064h 53 data sheet figure 17.11 dq2 vs. dq6 note dq2 toggles only when read at an address within an erase-suspended se ctor. the system may use oe# or ce# to toggle dq2 and dq6. 17.5 temporary sector unprotect note not 100% tested. figure 17.12 temporary sector unprotect timing diagram enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing parameter description all speed options jedec std unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb
54 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet figure 17.13 sector/sector block protec t and unprotect timing diagram note * for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. 17.6 alternate ce# controlled erase and program operations note 1. not 100% tested. 2. see erase and programming performance on page 56 for more information. sector group protect: 150 s sector group unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect/unprotect verify v id v ih parameter speed options jedec std. description 55 60 70 90 unit t avav t wc write cycle time (note 1) min55557090ns t avwl t as address setup time min 0 ns t elax t ah address hold time min30354045ns t dveh t ds data setup time min30354045ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 25 25 40 45 ns t ehel t cph ce# pulse width high min 25 25 30 ns t whwh1 t whwh1 programming operation (note 2) byte typ 5 s word typ 7 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) ty p 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.4 sec
september 8, 2009 s29jl064h_00_a8 s29jl064h 55 data sheet figure 17.14 alternate ce# controlled write (erase/program) operation timings notes 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy
56 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 18. erase and programming performance notes 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 100,000 cycles; checkerboard data pattern. 2. under worst case conditions of 90 c, v cc = 2.7 v, 1,000,000 cycles. 3. the typical chip programming time is consi derably less than the maximum chip programming time listed, since most bytes progra m faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 10.1 on page 36 for further information on command definitions. 6. the device has a minimum cycling endurance of 100,000 cycles per sector. 19. tsop & bga pin capacitance notes 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time 0.4 5 sec excludes 00h programming prior to erasure (note 4) chip erase time 56 sec byte program time 5 150 s excludes system level overhead (note 5) word program time 7 210 s accelerated byte/word program time 4 120 s chip program time (note 3) byte mode 42 126 sec word mode 28 84 accelerated chip programming time 10 30 sec parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf fine-pitch bga 4.2 5.0 pf c out output capacitance v out = 0 tsop 8.5 12 pf fine-pitch bga 5.4 6.5 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf fine-pitch bga 3.9 4.7 pf
september 8, 2009 s29jl064h_00_a8 s29jl064h 57 data sheet 20. physical dimensions 20.1 fbe063?63-ball fine-pitch ball grid array (bga) 12 x 11 mm package dwg rev af; 10/99
58 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 20.2 ts 048?48-pin standard tsop dwg rev aa; 10/99
september 8, 2009 s29jl064h_00_a8 s29jl064h 59 data sheet 21. revision history 21.1 revision a (january 22, 2004) initial release. 21.2 revision a1 (march 26, 2004) removed latchup characteristics section. 21.3 revision a 2 (april 28, 2004) updated data sheet status from preliminary to data sheet . 21.4 revision a3 (september 16, 2004) in-system sector protec t/unprotect algorithms corrected wait time in f ourth step of flowchart. autoselect codes corrected secured silicon indicator bit data on dq7 to dq0. command definitions corrected secured silicon se ctor factory protect da ta in fourth bus cycle. 21.5 revision a4 (june 28, 2005) added statement regarding new fbga designs to first page. updated trademark. ordering information added new fbga design statement. reformatted valid combinations table. sector / sector block protection and unprotection reformatted table 6 to fit on one page. operating ranges removed extended operating range. dc characteristics reformatted cmos compatible table columns. ac characteristics reformatted erase and program operations table columns. 21.6 revision a5 (june 6, 2007) removed the 7 inch tape and reel packing type. 21.7 revision a6 (august 10, 2007) dc characteristics changed v lko minimum, typical, and maximum values.
60 s29jl064h s29jl064h_00_a8 september 8, 2009 data sheet 21.8 revision a7 (september 19, 2007) s29jl064h autoselect codes, (high voltage method) table deleted code for 'customer locked' under column "dq7 to dq0" 21.9 revision a8 (september 8, 2009) in-system sector protect/unprotect algorithms updated figure secured silicon sector flash memory region modified section word/byte configuration (byte#) changed t fhqv condition from min. to max
september 8, 2009 s29jl064h_00_a8 s29jl064h 61 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004-2009 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse?, ornand?, ecoram? and combinations thereof, are trademar ks and registered trademarks of spansion llc in the united states and other count ries. other names used are for informati onal purposes only and may be trademarks of their respective owners.

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